Project TEC2005-05101, funded by
The down-scaling of Si CMOS devices issues scientific and technological challenges for the design and fabrication of integrated circuits. Key aspects to improve are the control of dopant profiles in ultra-shallow junctions and very short channels in MOSFETs and the development of new dielectric materials needed for the MOS gate. In this project we will carry out atomistic simulations of ion implantation and annealing, to adequately predict the dopant profiles, and electrical characterization of high-k dielectrics, to study their properties and performance. Our research is focused on the development and improvement of atomistic models for defect and dopant interactions, which are key in the definition of the final carrier profiles. The extension of the model to amorphous Si and stressed Si is needed as those materials are considered the most plausible option for the achievement of low-resistivity ultra-shallow junctions. Predictive and computationally efficient models will be developed and used for the analysis and optimization of ion implantation and thermal, flash and laser annealing processes. On the other hand, electrical properties and microscopic defects in high-k dielectrics grown by Atomic Layer Deposition will be characterized to establish the technological parameters for the fabrication of high purity layers. All these fields have open questions which are critical for the solution of the technological challenges set by the International Technology Roadmap for Semiconductors for the achievement of the 45nm node and beyond.