Atomistic simulation of defects in Ge: from materials properties to technological processes

Project VA011A09, funded by Logo JCyL

A high carrier mobility is a key feature to continue the downscaling of electronic devices and the subsequent improvement of the performance of integrated circuits. Although strained structures have been used to improve carrier mobility in Si beyond the 90 nm node, other high mobility materials are foreseen to partially substitute Si in the channel region of transistors beyond the 22 nm node. Ge is the most promising candidate because of its properties and the fact that Ge technology is compatible with the well established Si technology. However, many challenges have to be overcome, such as a better characterization of the material and an improvement in Ge process technology for the fabrication of integrated circuits. In this project atomistic simulation techniques (molecular dynamics and kinetic Monte Carlo) are used to deal with those aspects related to the defects induced by ion implantation into Ge. We will analyze the mechanisms underlying the interactions between defects and we will characterize their energetic parameters, as a starting point for the development of models that can be applied for process simulation. Our aim is the scientific progress in the characterization of Ge that can provide the guidelines for the technological development of future integrated circuits generations.