Study of advanced technological processes for manufacturing nanometric electronic devices through predictive simulation techniques

Project VA119G18, funded by Logo JCyL

The manufacturing technology of silicon integrated circuits faces great challenges. In order to continue during the next years with the scaling of electronic devices up to the 5 nm node, it is necessary to control the epitaxial growth of thin layers of SiGe with high Ge content. The lattice mismatch between Si and Ge makes difficult the generation of flat films at the atomic level, which negatively affects the characteristics of the devices. Beyond the 5 nm node silicon technology might not be longer effectively used. Molecular Electronics emerges as a possible alternative through the design and synthesis of molecules with specific electronic properties that can replace conventional silicon devices. To approach the study of these technological processes, the use of atomistic simulation techniques with predictive capacity becomes fundamental. The atomistic modeling that we propose in the present project can provide a detailed description of the processes and reveal the underlying physical mechanisms, in order to provide solutions to incoming technological problems.