10-bit, 40-Ms/s, 12-mW, Pipeline ADC
 

• Documents
• Slides
• Design
• First measurements

• Schematics
• Cell Hierarchy
• Cell schematics

• Layout snapshots

• Photograps
• ADC1.jpg
• ADC2.jpg

• Performance Tests
• Experimental Setup
• DNL  and INL
• Single Tone (20 KHz )
• Intermodulation (100KHz) (10 MHz)
• SNR and SNDR (3.578 MHz)

• Performance Summary

Vdd	2.5 V
Technology	0.25 um CMOS
Chip Area	1.5 x 0.88 mm2
Sampling Rate	40 MHz
Resolution	10 bits
Latency	300 ns (12 cycles)
Input Range	±1.6 V, differential
ADC Power	11.7 mW (core)
Pin Drivers Power (3.3 V)	1.3 mW (74AHC541 load)
DNL (max)	0.46 LSB
INL (max)	0.68 LSB
SNR	58.5 dB @ 20 KHz
SNDR	56.7 dB @ 20 KHz
Input Offset	1.3 mV