The DPLL block accounts for the clock recovery from the demodulator output. But currently no clock signal is generated. Instead the DPLL routine returns when the demodulator output shows a valid bit. A new call to the DPLL routine does not return until a new bit has arrived.
The DPLL routine uses the ``bit-phase'' concept. The bit-phase is an static 16 bit integer variable that can be incremented in a circular fashion. For each demodulator sample the bit-phase is incremented an amount that is related to the data rate and the sampling frequency. When the bit-phase overflows the DPLL routine returns.
In order to get the bit-phase variable synchronized with the incoming bits some feedback is needed. In our scheme the demodulator output must change only when the bit-phase is around its middle range value, that is 32768, so, if a bit change is detected before this bit-phase value, the bit-phase is advanced 1/32 of its total value. If the bit change takes place after the middle bit-phase value, the bit-phase is delayed 1/32 of its total value. This feedback try to set the bit change around the middle bit-phase value, and thus, when the DPLL routine returns, we are around the center of the bit time.