// 4-bit Binary Counter with Reset
// (See Figure 5-10)

module count_4_r_v (CLK, RESET, EN, Q, CO);
   input CLK, RESET, EN;
   output [3:0] Q;
   output CO;

reg [3:0] count;
assign Q = count;
assign CO = (count == 4'b1111 && EN == 1'b1) ? 1 : 0; 
always@(posedge CLK or posedge RESET)
   begin
   if (RESET)
      count <= 4'b0;
   else if (EN)
         count <= count + 1;
   end
endmodule