// Sequence Recognizer: Verilog Process Description
// (See Figure 4-21 for state diagram)
module seq_rec_v(CLK, RESET, X, Z);
   input CLK, RESET, X;
   output Z;
   reg [1:0] state, next_state;
      `define A	'b00
      `define B	'b01
      `define C	'b10
      `define D	'b11
   reg Z;

// state register: implements positive edge-triggered
// state storage with asynchronous reset.
always @(posedge CLK or RESET)
begin
   if (RESET)
      state <= `A;
   else
      state <= next_state;
end

// next state function: implements next state as function
// of X and state
always @(X or state) 
begin
   case (state)
      `A: next_state = X ? `B : `A;
      `B: next_state = X ? `C : `A;
      `C: next_state = X ? `C : `D;
      `D: next_state = X ? `B : `A;
   endcase
end

// output function: implements output as function
// of X and state
always @(X or state) 
begin
   case (state)
      `A: Z = 0;
      `B: Z = 0;
      `C: Z = 0;
      `D: Z = X ? 1 : 0;
   endcase
end
endmodule