// Positive Edge-Triggered D Flip-Flop with Reset:
// Verilog Process Description

module dff_v(CLK, RESET, D, Q, Q_n);
   input CLK, RESET, D;
   output Q, Q_n;
   reg state;

   assign Q = state;
   assign Q_n = ~ state;
  
always @(posedge CLK or posedge RESET)
begin
   if (RESET)
      state <= 0;
   else
      state <= D;
end
endmodule