// 4-bit Adder: Hierarchical Dataflow/Structural
// (See Figures 3-26 and 3-27 for logic diagrams)

module half_adder_v(x, y, s, c);
   input x, y;
   output s, c;

assign s = x ^ y;
assign c = x & y;

endmodule

module full_adder_v(x, y, z, s, c);
   input x, y, z;
   output s, c;

   wire hs, hc, tc;

   half_adder_v HA1(x, y, hs, hc),
                HA2(hs, z, s, tc);
      assign c = tc | hc;

endmodule


module adder_4_v(B, A, C0, S, C4);
   input[3:0] B, A;
   input C0;
   output[3:0] S;
   output C4;
	
   wire[3:1] C;


   full_adder_v Bit0(B[0], A[0], C0, S[0], C[1]),
                Bit1(B[1], A[1], C[1], S[1], C[2]),
                Bit2(B[2], A[2], C[2], S[2], C[3]),
                Bit3(B[3], A[3], C[3], S[3], C4);
endmodule