// 4-to-1 Line Multiplexer: Dataflow Verilog Description
// (See Figure 3-13 for logic diagram)
module multiplexer_4_to_1_tf_v(S, D, Y);
   input [1:0] S;
   input [3:0] D;
   output Y;

   assign Y = S[1] ? (S[0] ? D[3] : D[2]) :
                     (S[0] ? D[1] : D[0]) ;
endmodule