// 4-to-1 Line Multiplexer: Dataflow Verilog Description
// (See Figure 3-13 for logic diagram)
module multiplexer_4_to_1_cf_v(S, D, Y);
   input [1:0] S;
   input [3:0] D;
   output Y;

   assign Y = (S == 2'b00) ? D[0] :
              (S == 2'b01) ? D[1] :
              (S == 2'b10) ? D[2] :
              (S == 2'b11) ? D[3] : 1'bx ;
endmodule