// 2-to-4 Line Decoder: Structural Verilog Description
// (See Figure 3-13 for logic diagram)
module decoder_2_to_4_st_v(E, A0, A1, D0, D1, D2, D3);
   input E, A0, A1;
   output D0, D1, D2, D3;

   wire not_A0, not_A1;

   not 
      go(not_A0, A0),
      g1(not_A1, A1);

   nand
      g2(D0, not_A0, not_A1, E),
      g3(D1, A0, not_A1, E),
      g4(D2, not_A0, A1, E),
      g5(D3, A0,A1, E);

endmodule