-- 2-to-4 Line Decoder: Dataflow VHDL Description
-- (See Figure 3-13 for logic equations)
-- Use library, use, and entitry entries from 2_to_4_decoder_st;

library ieee, lcdf_vhdl;
use ieee.std_logic_1164.all, lcdf_vhdl.func_prims.all;
entity decoder_2_to_4 is
   port(E, A0, A1: in std_logic;
        D0, D1, D2, D3: out std_logic);
end decoder_2_to_4;

architecture dataflow_1 of decoder_2_to_4 is

signal not_A0, not_A1: std_logic;
begin
   not_A0 <= not A0;
   not_A1 <= not A1;
   D0 <= not ( not_A0 and not_A1 and E);
   D1 <= not ( A0 and not_A1 and E);
   D2 <= not ( not_A0 and A1 and E);
   D3 <= not ( A0 and A1 and E);   
end dataflow_1;